Semiconductor switches are utilized in electronic circuits to control when a signal is allowed to propagate from one node to another. An implementation of such a switch in CMOS technology is the transmission gate (examples shown in FIGS. 1A and 1B), comprising NMOS and PMOS transistors connected in parallel for the purpose of allowing good conductivity for a wide signal voltage range. There are a number of different ways in which combinations of transistors can be connected together to implement a switch function; however, they all perform the same basic function of connecting two nodes when “on”, and isolating the two nodes when “off”. For DC signals inside an intended operating range, a switch appears like a resistor, the impedance depending on the architecture used and the dimensions of the transistors. There can also be dependence on the DC level of the signal for most architectures.
In FIG. 1A is shown a data switch of prior art comprising an N-channel transistor 10 and a P-channel transistor 11 connected in parallel, where the sources of the two transistors are connected together to form a data input A and the drains of the two transistors are connected to form data output B. An ON signal, a high logic signal, is applied to the gate of the N-channel transistor 10 and through an inverter circuit 12 to the gate of the P-channel transistor 11. To turn off the switch an off signal, which is a low logic signal, is applied to the gate of the N-channel transistor and through the inverter circuit to the gate of the P-channel transistor.
In FIG. 1B is a second data switch of prior art where a second parallel connected pair of transistors, an N-channel transistor 15 and a P-channel transistor 16, are connected in tandem 13 with a first pair of transistors 10 and 11. An N-channel transistor 14 is used to ground the tandem connection 13 to insure isolation between A and B.
A semiconductor switch presents a resistance to AC signals inside the intended operating range, but parasitic capacitance is also present. The impedance of the parasitic capacitive will present an AC path to the power supplies and chip substrate, and will ultimately cause signal attenuation at higher frequencies. In addition there will be capacitive impedance between the two sides of the switch that will cause some signal propagation when in the “off” state, thus reducing the isolation of the switch against higher frequency signals. A disadvantage of prior-art switch design shown in FIG. 1A is that lower resistive impedance in the “on” state dictates larger transistors. Larger transistors inherently include larger unwanted capacitances; therefore strong switches with low on-resistance also have larger parasitic capacitances, which limit the maximum frequency of a switched signal.
The purpose of the switches in FIGS. 1A and 1B is to make the voltage at node B equal to the voltage at node A while in the “on” state. Any change in the signal voltage at nodes A and B will require the total sum of all parasitic capacitances to be charged, or discharged, by a charge, ΔQ, equal to the sum of capacitances multiplied by the change in voltage, ΔQ=C·ΔV. Thus the faster the signal frequency, the higher the current required to charge and discharge the parasitic capacitances, i=C·dv/dt.
US 2006/0164164 A1 (Rogers et al.) is directed to compensating for parasitic capacitances in a VCA circuit. U.S. Pat. No. 8,400,848 B2 (Fujimura) is directed to a bit line capacitance compensation capacitor, which compensates the capacitance of the bit line, and a peripheral capacitance compensation capacitor, which compensates the peripheral capacitance of the bit line. In U.S. Pat. No. 8,344,808 B2 (Samavedamet al.) a capacitance compensation is directed to using a compensation device coupled to a gain device. U.S. Pat. No. 8,344,802 B2 (Huang et al.) is directed to an operational amplifier device capable of using transmission gates for capacitance compensation. U.S. Pat. No. 6,462,611 B2 (Shigehara et al.) is directed to body effect compensation for electronic switches connected between two terminals. In U.S. Pat. No. 6,150,884 (Fattaruso) an improved operational amplifier circuit with nested transconductance is directed to capacitance compensation.